1. Field
The present invention relates generally to semiconductor manufacturing and, more particularly, to apparatus for aligning electrodes in a process chamber to define regions of process exclusion and of process performance in the process chamber for manufacturing semiconductor wafers.
2. Description of the Related Art
Vacuum processing chambers have been used for etching materials from substrates and for deposition of materials onto substrates. The substrates have been semiconductor wafers, for example. In general, accurate processing (and thus high yields of devices) is expected to occur in a central area of the wafer. Numerous difficulties are experienced in attempting to accurately process the wafer on a portion of a top, or upper, surface of the wafer, wherein that portion is between the central area and a peripheral edge of the wafer that surrounds the central area. Such difficulties are significant enough that an “edge exclusion area” has been defined between the central area and that peripheral edge of the wafer surrounding that central area. No attempt is made to provide acceptable devices in that edge exclusion area.
Additionally, during the desired processing of the central area, undesired deposits, materials, or process-by-products (collectively “undesired materials”), accumulate or result on the edge exclusion area of the upper surface of the wafer, and on a peripheral edge area of the peripheral edge of the wafer, and below the peripheral edge area onto a bottom area of an opposite (bottom) surface of the wafer. Those three areas are not to be processed to form devices. The edge exclusion area, the edge area, and the bottom area are referred to collectively as the “edge environ”. These undesired materials may generally accumulate on the edge environ. The accumulation may be so extensive that the desired processing of the central area must be interrupted because, in general, it is desired to keep the edge environ substantially clean, so as to avoid flaking of material particulates that may redeposit back onto the active device regions on the upper surface of the wafer. Such flaking can occur during any number of wafer handling or transport operations, and thus, it is a general desire that the edge environ be periodically cleaned (e.g., etched) or monitored for cleaning (i.e., etching) during the numerous processing operations used to fabricate integrated circuit device chips, from the processed wafers. The desired processing of the central area has been interrupted to perform such periodic cleaning in an attempt to remove the undesired materials from the edge environ, e.g. from the entire edge environ, and e.g., to perform such removal without damaging the devices.
In view of the foregoing, there is a need to assure that such needed apparatus is accurately aligned before use, so that in use the apparatus results in accurate (e.g., uniform) removal of the undesired materials from the entire edge environ, without removing materials from or otherwise damaging the central area.